FE RTL Designer / SoC integration

Vertical Compute is a pioneering company developing proprietary Vertical Integrated Memory (VIM™) chiplets to overcome AI hardware bottlenecks. We are seeking a skilled Front-End RTL Designer to join our hardware team and lead the integration of our innovative AI accelerators.

Key responsibilities

• Lead top-level SoC and chiplet integration by incorporating internal and third-party IPs into high-performance AI accelerators.
• Integrate proprietary VIM™ technology with compute engines to maximize system throughput and bandwidth efficiency.
• Partner with functional verification teams to build environments, debug RTL issues, and ensure comprehensive design coverage.
• Collaborate with physical design teams to optimize Power, Performance, and Area (PPA) through synthesis, timing closure, and floorplanning support.

Requirements

• Solid professional background in front-end RTL design and top-level SoC or chiplet integration.
• Degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related technical field.
• Strong proficiency in SystemVerilog or Verilog and experience working across verification and physical design domains.
• Excellent communication and collaborative problem-solving skills suitable for a fast-paced, innovative environment.
• Fluency in English with effective written and verbal communication capabilities.

What we offer

• The opportunity to take direct ownership of the hardware foundation powering the next generation of AI compute.
• A collaborative and innovative team environment dedicated to pushing the boundaries of memory and compute integration.
• Engagement in a high-impact role that bridges the gap between semiconductor physics and commercial AI hardware reality.